Application of Digitally Controlled Phase Shifter Based on Ring Oscillator in Frequency Synthesizer and Pulse Width Modulator

Direct digital frequency synthesizer based on accumulators and phase registers, normally use fixed period clock signals. This results in synthesized signals having instantaneously varying time period. A technique of time period modification of the clock signal is proposed here to synthesized fixed period signal. The proposed technique is verified via simulation and hardware experiment. INTRODUCTION Frequency synthesizers are important building blocks of communication systems. Modern wireless communication systems demand frequency synthesizers of high resolution and fast frequency switching speed. The direct digital frequency synthesizers (DDFSs) [1] are able to provide fine step size and required first frequency switching because they have no feedback loop. The disadvantage of the DDFS is large power consumption due to the presences of ROM look-up table in the synthesizer circuit. Therefore the efforts have been made to reduce the ROM size or to eliminate it from FS [2] circuit without degrading the performance of the synthesizer. This paper presents accumulator and phase resister based FS [3], where the most significant bit (MSB) of the phase register gives the synthesized output signal. Conventionally, applying fixed period clock signal at the phase resister, one get the synthesized signal of instantaneously varying time period. To get fixed period synthesized signal we have been used suitable phase modulated clock signal at the clock input of the phase resister. A phase accumulator-based frequency divider, shown in Fig.-1, is often used in conventional direct digital frequency synthesizer (DDFS) circuits [4]. An n-bit accumulator adds with its output stored in an n-bit phase register (PR) with a binary data k (frequency control word) once in every Tc time. Tc is the period of the s PR. The period of the synthesized output signal taken from the maximum significant be, on an average, Tr = (2/k)Tc . The value of k should be less than 2 in practice. If c represents the integral part of to (c+1)Tc. If the system starts from a reset condition of the PR and k is a number, w form, 2, where t is positive integer less than (n-1), the content of the PR will be r wh Cout is obtained). In this situation one can write (c+1)k = 2 + r The synthesized signal is a train of rectangular wave whose period fluctu (c+1)Tc and out of k cycles of the output, r cycles will have a period cTc while the (c+1)Tc . The period of the output signal (Tr) is a weighted average of cTc and (c+1)T Tr = [rcTc + (k-r)(c+1)Tc ]/k